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ADVANCED INFORMATION
CY7C1331 CY7C1332
64K x 18 Synchronous Cache 3.3V RAM
Features
* Supports 66-MHz PentiumTM processor cache systems with zero wait states * Single 3.3V power supply * 64K by 18 common I/O * Fast clock-to-output times -- 8.5 ns * Two-bit wraparound counter supporting the Pentium and 486 burst sequence (7C1331) * Two-bit wraparound counter supporting linear burst sequence (7C1332) * Separate processor and controller address strobes * Synchronous self-timed write * Direct interface with the processor and external cache controller * Asynchronous output enable * JEDEC-standard pinout * 52-pin PLCC and PQFP packaging
Functional Description
The CY7C1331 and CY7C1332 are 3.3V 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1331 is designed for Intel Pentium and i486 CPU-based systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1332 is architected for processors with linear burst sequences. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and an asynchronous output enable input provide easy control for bank selection and output three-state control.
LogicBlockDiagram
18 DATA IN REGISTER ADDR REG 9 14 16 2 ADV ADV LOGIC 2 64K X 9 64K X 9 RAM ARRAY RAM ARRAY 9 DQ8 DQ9 VCCQ VSSQ DQ10 DQ11 DQ12 DQ13 VSSQ VCCQ DQ14 DQ15 [2] DP1 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Configuration
PLCC Top View
WH WL ADSC ADSP ADV CLK A6 A7 CS A 8 A 9 A10 OE
16 A15 - A0
14
CLK ADSP ADSC CS WH WL TIMING CONTROL
WH
WL 9 9
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C1331 7C1332 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 A1 A0 GND V CC A 15 A14 A13 A12 A11 A5 A4 A3 A2
DP0 DQ7 DQ6 VCCQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VCCQ DQ1 DQ0
[2]
18 DQ15 - DQ0 DP1 - DP0 OE 1331- 2 1331-1
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA)
Notes: 1. DP0 and DP1 are functionally equivalent to DQx. Pentium is a trademark of Intel Corporation.
Commercial Military
7C1331-8 7C1332-8 8.5 200
7C1331-10 7C1332-10 10 200
7C1331-12 7C1332-12 12 170 200
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 December 1992 - Revised April 1995
ADVANCED INFORMATION
Functional Description (continued) Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CS is LOW and (2) ADSP is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at A 0 through A15 is loaded into the address register and address advancement logic and delivered to the RAM core. The write signal is ignored in this cycle because the cache tag or other external logic uses this clock period to perform address comparisons or protection checks. If the write is allowed to proceed, the write input to the CY7C1331 and CY7C1332 will be pulled LOW before the next clock rise. ADSP is ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information presented at DQ0 - DQ15 and DP0 - DP1 will be written into the location specified by the address advancement logic. WL controls the writing of DQ0 - DQ7 and DP0 while WH controls the writing of DQ8 - DQ15 and DP1. Because the CY7C1331 and CY7C1332 are common-I/O devices, the output enable signal (OE) must be deasserted before data from the CPU is delivered to DQ0 - DQ15 and DP0 - DP1. As a safety precaution, the appropriate data lines are three-stated in the cycle where WH, WL, or both are sampled LOW, regardless of the state of the OE input. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC is LOW, and (3) WH or WL are LOW. ADSC triggered accesses are completed in a single clock cycle. The address at A0 through A15 is loaded into the address register and address advancement logic and delivered to the RAM core. Information presented at DQ0 - DQ15 and DP0 - DP1 will be written into the location specified by the address advancement logic. WL controls the writing of DQ0 - DQ7 and DP0 while WH controls the writing of DQ8 - DQ15 and DP1. Since the CY7C1331 and the CY7C1332 are common-I/O devices, the output enable signal (OE) must be deasserted before data from the cache controller is delivered to the data lines. As a safety precaution, the appropriate data lines are three-stated in the cycle where WH, WL, or both are sampled LOW, regardless of the state of the OE input.
CY7C1331 CY7C1332
Single Read Accesses
A single read access is initiated when the following conditions are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC is LOW, and (3) WH and WL are HIGH. The address at A0 through A15 is stored into the address advancement logic and delivered to the RAM core. If the output enable (OE) signal is asserted (LOW), data will be available at the data outputs a maximum of 8.5 ns after clock rise.
Burst Sequences
The CY7C1331 provides a 2-bit wraparound counter, fed by pins A0 - A1, that implements the Intel 80486 and Pentium processor address burst sequence (see Table 1). Note that the burst sequence depends on the first burst address. Table 1. Counter Implementation for the Intel Pentium/80486 Processor's Sequence First Second Third Fourth Address Address Address Address A X + 1, Ax AX + 1, Ax AX + 1, Ax AX + 1, Ax 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 The CY7C1332 provides a two-bit wraparound counter, fed by pins A0 - A1, that implements a linear address burst sequence (see Table 2). Table 2. Counter Implementation for a Linear Sequence First Second Third Fourth Address Address Address Address A X + 1, Ax AX + 1, Ax AX + 1, Ax AX + 1, Ax 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Application Example
Figure 1 shows a 512-Kbyte secondary cache for a hypothetical 3.3V, 66-MHz Pentium or i486 processor using four CY7C1331 cache RAMs.
512 KB
66-MHz OSC
CLK ADR DATA PENTIMUM OR i486 PROCESSOR ADS
CLK ADR DATA ADSP ADSC ADV OE WH, WL WH, WL 2 2 2 WH2 , WL2 2 WH3 , WL3 INTERFACE TO MAIN MEMORY WH, WL WH, WL 7C1331
CLK ADR CACHE TAG DATA MATCH DIRTY VALID
WH1 , CLK ADSC ADV OE WH0 , WL1 WL0 ADR DATA ADSP CACHE CONTROLLER MATCH DIRTY VALID
1331- 3
Figure 1. Cache Using Four CY7C1331s.
2
ADVANCED INFORMATION
Pin Definitions
Signal Name VCC VCCQ GND VSSQ CLK A15 - A0 ADSP ADSC WH WL ADV OE CS DQ15-DQ0 DP1-DP0 Input Input Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Type # of Pins 1 4 1 4 1 16 1 1 1 1 1 1 1 16 2 +3.3V Power +3.3V (Outputs) Ground Ground (Outputs) Clock Address Address Strobe from Processor Address Strobe from Cache Controller Write Enable - High Byte Write Enable - Low Byte Advance Output Enable Chip Select Regular Data Parity Data Description
CY7C1331 CY7C1332
Pin Descriptions
Signal Name CLK I/O I Description Clock signal. It is used to capture the address, the data to be written, and the following control signals: ADSP ADSC, WH, , WL, CS, and ADV. It is also used to advance the on-chip auto-address-increment logic (when the appropriate control signals have been set). Sixteen address lines used to select one of 64K locations. They are captured in an on-chip register on the rising edge of CLK if ADSP or ADSC is LOW. The rising edge of the clock also loads the lower two address lines, A1 - A0, into the on-chip auto-address-increment logic if ADSP or ADSC is LOW. Address strobe from processor. This signal is sampled at the rising edge of CLK. When this input and/or ADSC is asserted, A0-A15 will be captured in the on-chip address register. It also allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. If both ADSP and ADSC are asserted at the rising edge of CLK, only ADSP will be recognized. The ADSP input should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH.
Pin Descriptions (continued)
Signal Name ADSC I/O I Description Address strobe from cache controller. This signal is sampled at the rising edge of CLK. When this input and/or ADSP is asserted, A0-A15 will be captured in the on-chip address register. It also allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. The ADSC input should not be connected to the ADS output of the processor. Write signal for the high-order half of the RAM array. This signal is sampled by the rising edge of CLK. If WH is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of DQ15 - DQ8 and DP 1 from the on-chip data register into the selected RAM location. There is one exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write signal, WH, is ignored. Note that ADSP has no effect onWH if CS is HIGH. Write signal for the low-order half of the RAM array. This signal is sampled by the rising edge of CLK. If WL is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of DQ7 - DQ0 and DP 0 from the on-chip data register into the selected RAM location. There is one exception to this. If ADSP ,WL, and CS are asserted (LOW) at the rising edge of CLK, the write signal, WL, is ignored. Note that ADSP has no effect on WL if CS is HIGH.
A15-A0
I
WH
I
ADSP
I
WL
I
3
ADVANCED INFORMATION
Pin Descriptions (continued)
Signal Name
ADV
CY7C1331 CY7C1332
Pin Descriptions (continued)
Signal Name I/O Description
I/O I
Description Advance. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically increments the two-bit on-chip auto-address-increment counter. In the CY7C1332, the address will be incremented linearly. In the CY7C1331, the address will be incremented according to the Pentium/486 burst sequence. This signal is ignored if ADSP or ADSC is asserted concurrently with CS. Note that ADSP has no effect on ADV if CS is HIGH. Chip select. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW, the SRAM is deselected. If CS is LOW and ADSC or ADSP is LOW, a new address is captured by the address register. If CS is HIGH, ADSP is ignored. Output enable. This signal is an asynchronous input that controls the direction of the data I/O pins. If OE is asserted (LOW), the data pins are outputs, and the SRAM can be read (as long as CS was asserted when it was sampled at the beginning of the cycle). If OE is deasserted (HIGH), the data I/O pins will be three-stated, functioning as inputs, and the SRAM can be written.
Bidirectional Signals DQ15-DQ0 I/O Sixteen bidirectional data I/O lines. DQ15 DQ8 are inputs to and outputs from the high-order half of the RAM array, while DQ7 - DQ0 are inputs to and outputs from the low-order half of the RAM array. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they carry the data read from the selected location in the RAM array. The direction of the data pins is controlled by OE: when OE is high, the data pins are three-stated and can be used as inputs; when OE is low, the data pins are driven by the output buffers and are outputs. DQ 15 DQ8 and DQ7 - DQ0 are also three-stated when WH and WL, respectively, are sampled LOW at clock rise. Two bidirectional data I/O lines. These operate in exactly the same manner as DQ15 - DQ0, but are named differently because their primary purpose is to store parity bits, while the DQs' primary purpose is to store ordinary data bits. DP1 is an input to and an output from the high-order half of the RAM array, while DP0 is an input to and an output from the lower-order half of the RAM array.
CS
I
OE
I
DP1-DP0
I/O
4
ADVANCED INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied ...............................................-55C to +125C Supply Voltage on VCC Relative to GND................ -0.5V to +3.6V DC Voltage Applied to Outputs in High Z State[2] ...............................................-0.5V to VCC + 0.3V DC Input Voltage[2] ...........................................-0.5V to VCC + 0.3V Current into Outputs (LOW) ......................................... 20 mA
CY7C1331 CY7C1332
Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Com'l Mil Ambient Temperature[3] 0C to + 70C -55C to + 125C VCC, VCCQ 3.3V 0.3V 3.3V 0.3V
Electrical Characteristics Over the Operating Range[4]
7C1331-8 7C1332-8 Parameter VOH VOL VIH VIL IX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current Output Short Circuit Current[5] VCC Operating Supply Current GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC=Max.,Iout=0mA, Com'l f=fMAX =1/tCYC Mil Test Conditions VCC = Min., IOH=-2.0 mA VCC = Min., IOL=2.0 mA 2.0 -0.3 -1 -5 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 -300 200 60 2.0 -0.3 -1 -5 Max. 7C1331-10 7C1332-10 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 -300 200 60 2.0 -0.3 -1 -5 Max. 7C1331-12 7C1332-12 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +5 -300 170 200 40 40 20 20 20 20 mA mA Min. Unit V V V V A A mA mA
Automatic CE Max. VCC, CS VIH, Com'l Power-Down Current - VIN VIH or VIN VIL, Mil TTL Inputs f=fMAX Automatic CE Power-Down Current -CMOS Inputs Max. VCC, CS VCC Com'l -0.3V, VIN VCC Mil -0.3V or VIN 0.3V, [6] f=fMAX
ISB2
Notes: 2. Minimum voltage equals - 2.0V for pulse durations of less than 20 ns. 3. TA is the "instant on" case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Capacitance[7]
Parameter CIN: Addresses CIN: Other Inputs COUT Description Input Capacitance Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Com'l Mil Com'l Mil Com'l Mil Max. 5 6 5 8 8 16 pF pF Unit pF
5
ADVANCED INFORMATION
AC Test Loads and Waveforms
R1 1179 OUTPUT Z0 =50 3.3V OUTPUT RL =50 VL =1.5V 5 pF INCLUDING JIG AND SCOPE R2 868
CY7C1331 CY7C1332
ALL INPUT PULSES 3.0V 10% GND 3 ns 90% 90% 10% 3 ns
(a)
(b)
1331-4 1331-5
Notes: 6. Inputs are disabled, clock is allowed to run at speed. 7. Tested initially and after any design or process changes that may affect these parameters.
Switching Characteristics Over the Operating Range[8]
7C1331-8 7C1332-8 Parameter tCYC tCH tCL tAS tAH tCDV tDOH tADS tADSH tWES tWEH tADVS tADVH tDS tDH tCSS tCSH tCSOZ tEOZ tEOV tWEOZ tWEOV Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-Up Before CLK Rise ADSP, ADSC Hold After CLK Rise WH, WL Set-Up Before CLK Rise WH, WL Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip Select Set-Up Chip Select Hold After CLK Rise Chip Select Sampled to Output High Z OE HIGH to Output High Z OE LOW to Output Valid WH or WL Sampled LOW to Output High Z WH or WL Sampled HIGH to Output Valid
[9, 10] [10] [9] [9]
7C1331-10 7C1332-10 Min. 15 6 6 2.5 0.5 Max.
7C1331-12 7C1332-12 Min. 20 8 8 2.5 0.5 Max. Unit ns ns ns ns ns 12 3 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 ns ns ns ns ns ns ns ns ns ns ns 7 7 6 7 12 ns ns ns ns ns
Description Clock Cycle Time
Min. 15 5 5 2.5 0.5
Max.
8.5 3 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2 2 6 6 5 5 8.5 3 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2 2
10
6 6 5 6 10
2 2
Notes: 8. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance as shown in (a) and (b) of AC Test Loads. 9. tCSOZ, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 10. At any given voltage and temperature, t WEOZ min. is less than tWEOV min.
6
ADVANCED INFORMATION
Switching Waveforms
Single Read [11]
tCH CLK tCSS CS tAS ADDRESS tADS ADSP [12] or ADSC t WES WH, WL [13] tCDV DATA OUT t WEH tADSH tAH tCSH tCL tCYC
CY7C1331 CY7C1332
tDOH
1331-7
Single WRite Timing: Write Initiated by ADSP
tCH CLK tCSS CS tAS ADDRESS tADS ADSP tWES WH, WL[13] tDS DATA IN tDH tWEH tADSH tAH tCSH tCL
DATA OUT tEOZ OE
1331-6
Notes: 11. OE is LOW throughout. 12. If ADSP is asserted while CS is HIGH, ADSP will be ignored. 13. ADSP has no effect on ADV, WH, and WL if CS is HIGH.
7
ADVANCED INFORMATION
Switching Waveforms (continued)
Single Write Timing: Write Initiated by ADSC
tCH CLK tCSS CS tAS ADDRESS tADS ADSC tWES WH, WL tDS DATA IN tDH tWEH tADSH tAH tCSH tCL
CY7C1331 CY7C1332
DATA OUT tEOZ
OE
1331-8
Burst Read Sequence with Four Accesses
CLK tCSS CS tAS ADDRESS tADS tADSH tAH tCSH
ADSP [12] or ADSC
tADVS ADV [13] tWES tWEH
tADVH
[13] WH, WL
OE tCDV DATA OUT DATA0 tDOH DATA1 DATA2 DATA3
1331-9
8
ADVANCED INFORMATION
Switching Waveforms (continued)
Output (Contolled by OE)
CY7C1331 CY7C1332
DATA OUT tEOZ OE
1331-10
tEOV
Write Burst Timing: Write Initiated by ADSC
CLK tCSS CS tWES WH,WL
[13]
tCSH
tWEH
OE tADS ADSP
[12 ]
tADSH
tADS ADSC tAS ADDR
tADSH
tAH
tADVS ADV
[13]
tADVH
tDS DATA DATA0
tDH DATA1 DATA2 DATA3
1331-11
9
ADVANCED INFORMATION
Switching Waveforms (continued)
Write Burst Timing Waveforms: Write Initiated by ADSP
CY7C1331 CY7C1332
CLK tCSS tCSH
CS
WH, L W [13]
OE
ADSC tADS ADSP [12] tAS ADDR tADVS tADVH ADV [13] tDS DATA tDH DATA1 DATA2 DATA3 tAH tADSH
DATA0
1331-12
Output Timing (Controlled by CS)
CLK tADS ADSC tADS tADSH tCSS tCSS CS tCDV DATA OUT
1331-13
tADSH
tCSH
tCSH
tCSOZ
10
ADVANCED INFORMATION
Switching Waveforms (continued)
Output Timing (Controlled by WH/WL)
CLK tADS tADSH tADS tADSH
CY7C1331 CY7C1332
ADSC and ADSP WH, WL
tWES
tWEH
tWEOZ DATA OUT
tWEOV
1331-14
Truth Table
Inputs CS H H H H H L L L X X X X ADSP X L L L L L H H H H H H ADSC L H H H H X L L H H H H ADV X H L H L X X X L L H H WH or WL X H H L L X H L L H L H CLK LH LH LH LH LH LH LH LH LH LH LH LH N/A Same address as previous cycle Incremented burst address Same address as previous cycle Incremented burst address External External External Incremented burst address Incremented burst address Same address as previous cycle Same address as previous cycle Address Operation Chip deselected Read cycle (ADSP ignored) Read cycle, in burst sequence (ADSP ignored) Write cycle (ADSP ignored) Write cycle, in burst sequence (ADSP ignored) Read cycle, begin burst Read cycle, begin burst Write cycle, begin burst Write cycle, begin burst Read cycle, begin burst Write cycle Read cycle
11
ADVANCED INFORMATION
Ordering Information
Speed (ns) 8.5 10 12 Ordering Code CY7C1331-8JC CY7C1331-8NC CY7C1331-10JC CY7C1331-10NC CY7C1331-12JC CY7C1331-12NC Package Name J69 N52 J69 N52 J69 N52 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack Commercial Commercial Operating Range Commercial
CY7C1331 CY7C1332
Speed (ns) 8.5 10 12
Ordering Code CY7C1332-8JC CY7C1332-8NC CY7C1332-10JC CY7C1332-10NC CY7C1332-12JC CY7C1332-12NC
Package Name J69 N52 J69 N52 J69 N52
Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack
Operating Range Commercial Commercial Commercial
Document #: 38-00223-B
12
ADVANCED INFORMATION
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
CY7C1331 CY7C1332
52-Lead Plastic Quad Flatpack N52
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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